Semiconductor integrated circuits usually include elements, such as transistors, disposed on a substrate. In order to electrically interconnect the elements to each other and/or to other circuits, electrically conducting connecting lines are disposed on the substrate. These connecting lines are made of polycrystalline silicon films, refractory metal films, refractory metal silicide films, refractory metal polycide films, aluminum films, or aluminum alloy films. Since recently developed semiconductor integrated circuits use increasing operating speeds, the electrical resistance of the connecting lines must be decreased. For this reason, multiple level interconnections made of aluminum or aluminum alloy films are popular. A multi-level interconnection employing aluminum films is described in "High Performance Multilevel Interconnection System With Stacked Interlayer Dielectrics By Plasma CVD And Bias Sputtering", by Abe et al, pages 4040-410, VMIC Conference, 1989.
FIG. 35(A) is a plan view and FIG. 35(B) is a cross-sectional view taken along line 35(B)--35(B) of FIG. 35(A) of a multi-level interconnection structure in an integrated circuit. In those figures, a dynamic random access memory (DRAM) cell 2 is a stacked structure disposed on a silicon substrate 1. A first dielectric layer 3 is disposed on the DRAM cell 2. A first electrically conducting interconnection layer 4 is disposed on part of the dielectric layer 3. A second dielectric layer 5 covers the first interconnection layer 4. A through hole 6 penetrates the second dielectric layer 5. A second electrically conducting interconnection layer 7 is disposed on the second dielectric layer 5 and is connected to the first interconnection layer 4 at the through hole 6. A third dielectric layer 8 covers the DRAM cell 2 and the first and second interconnection layers 4 and 7 to prevent moisture from reaching the DRAM cell 2. The second interconnection layer 7 includes a titanium nitride film 9 that directly contacts the second dielectric layer 5 and an aluminum alloy film 10. The stability of the connection between the first and second interconnection layers is important to ensure the reliability of the semiconductor integrated circuit.
A method of making the conventional multi-layer interconnection structure shown in FIGS. 35(A) and 35(B), particularly directed to the formation of the through hole 6, is explained in connection with FIGS. 36-44. In many multi-level interconnection structures, polycrystalline silicon, refractory metals, refractory metal silicides, refractory metal polycides, and aluminum are used in various combinations. However, in the method described below, each of the interconnection layers includes aluminum alloy films.
In FIG. 36, the DRAM cell 2 has already been fabricated and is disposed on the silicon substrate 1. A silicon oxide film 301 disposed on the surface of the substrate 1 electrically isolates the DRAM cell 2. The DRAM cell 2 includes a portion of the silicon oxide layer 301, a transfer gate electrode 302, a doped region 303 within the substrate 1, a word line 304, a storage node 305, a capacitor dielectric layer 306, an electrically conducting cell plate 307, and a dielectric layer 309. The word line 304 is disposed between the silicon oxide layer 301 and the dielectric layer 309. The transfer gate electrode 302 is disposed within the dielectric layer 309. The doped region 303 is disposed beneath part of the storage node 305 as well as in the substrate 1 on the opposite side of the transfer gate electrode 302.
As shown in FIG. 37, the first dielectric layer 3 is deposited on the dielectric layer 309 covering the DRAM cell 2. A contact hole 308 penetrating the first dielectric layer 3 and the dielectric layer 309 adjacent the transfer gate electrode 302 is opened using conventional photolithographic technology. As shown in FIG. 38, the first interconnection layer 4 is deposited on the first dielectric layer 3 and in the contact hole 308. The first interconnection layer 4 includes a titanium nitride (TiN) or a titanium tungsten alloy (TiW) film 310 contacting the first dielectric layer 3 and an aluminum alloy film 311 that may be Al--Si or Al--Si--Cu disposed on the film 310.
In many current semiconductor integrated circuits, structural elements have sub-micron dimensions. In these integrated circuits, the interconnection layers include two films, such as films 310 and 311, for several reasons. First, when aluminum contacts the doped part of the silicon substrate, an abnormal reaction, referred to an alloy spike, may occur. The alloy spike may penetrate the doped region to the substrate, resulting in current leakage. In order to prevent this reaction, an interconnection layer including two films is employed so that a titanium compound or alloy directly contacts the silicon substrate. Second, silicon in the aluminum alloy film 311 may be grown in solid-phase epitaxy rather than being homogeneously deposited, resulting in poor contacts. To prevent this undesirable growth, the first interconnection layer 4 includes the titanium alloy film 310. Third, dielectric layers are disposed on or near the aluminum interconnection structure. These films apply stress that can cause an aluminum interconnection to become electrically open, an effect called stress migration. The titanium alloy film 310 adjacent the aluminum alloy film 311 has a high resistance to stress migration.
As shown in FIG. 39, the first interconnection layer 4 is patterned by conventional photolithographic technology. After the patterning, as shown in FIG. 40, the second dielectric layer 5 is deposited on the first interconnection layer 4. The second dielectric layer 5 includes a silicon oxide film 321, an inorganic spin-on glass (SOG) film 322, and a second dielectric film 323. The films 321 and 323 are deposited by chemical vapor deposition (CVD). In that CVD method, a mixture of silane (SiH.sub.4) and oxygen (O.sub.2) or N.sub.2 O is employed at a temperature under 300.degree. C. to 450.degree. C. to deposit the dielectric films. Recently, silicon oxide films providing good step coverage have also been prepared using tetraethylorthosilicate (TEOS). The inorganic SOG film 322 is used to flatten the surface of the silicon oxide film 321 and usually includes Si(OH).sub.4 as the principal ingredient. After applying the SOG, the film is baked at a temperature of 400.degree. C. to 450.degree. C. to convert the SOG material into a silicon oxide film. The SOG film 322 is highly hygroscopic so that if the SOG film 322 is exposed on the side wall of the through hole, it may release a gas. For this reason, dry etching is usually employed to form through holes to avoid exposing the surface of the SOG film 322.
As shown in FIG. 41, the through hole 6 is formed using conventional photolithographic technology to expose a portion of the surface of the aluminum alloy film 311 of the first interconnection layer 4. A layer of photoresist 324 is deposited on the silicon oxide film 323 and patterned to expose the area where the through hole 6 is to be formed. Thereafter, a portion of the second dielectric layer 5 comprising the silicon oxide layers 321 and 323 is removed using the tapered etching method. In that method, wet etching with a HF/NH.sub.4 F solution is followed by reactive ion etching (RIE) in a mixture of CHF.sub.3 and oxygen. Subsequently, the photoresist 324 and the products of the etching steps are removed.
During the etching process forming the through hole 6, the surface of the first interconnection layer 4 is exposed to the plasma of CHF.sub.3 and oxygen which includes fluorine. As a result, a portion of the aluminum alloy film 311 to a depth of about ten nanometers is contaminated with fluorine and oxygen. In order to remove the thin contaminated layer, layer 251 of FIG. 41, argon sputter etching is carried out, as indicated in FIG. 42. Removal of the contaminated layer 251 produces a more stable contact resistance in the subsequently formed structure. Thereafter, the second interconnection layer 7, including the titanium nitride film 9 and the aluminum alloy film 10, is deposited as shown in FIG. 43. The titanium nitride film 9 resists stress migration that can cause open circuits in the second interconnection layer due to the overlying dielectric layers. The first and second interconnection layers 5 and 7 remain in good contact, providing good resistance against electromigration and stress migration. The aluminum alloy film 10 and the titanium nitride film 9 are patterned using the same photolithographic technology employed for patterning the first interconnection layer 4. After the second interconnection layer 7 is deposited, it is heated at 400.degree. C. to 450.degree. C. in order to establish an electrical contact between the first and second interconnection layers 4 and 7 within the through hole 6.
Finally, referring to FIG. 44, the third dielectric layer 8, which is silicon oxide or silicon nitride, is deposited on the second interconnection layer 7 by CVD to provide moisture protection.
The conventional multi-layer interconnection structure described has a number of problems. As the interconnection is reduced in size, the diameter of the through hole 6 becomes smaller. When that diameter is less than about a micron, the electrical contact formed by way of the through hole 6 can become unstable or unreliable. FIG. 45(A) is a plan view of a contact in a double layer interconnection. FIG. 45(B) is a cross-sectional view taken along line 45(B)--45(B) of FIG. 45(A). In that structure, a first narrow interconnection 12 is connected to a second thin interconnection 14 through a through hole 16, all at the right side of FIGS. 45(A) and 45(B). On the left side of FIGS. 45(A) and 45(B), corresponding to a buffer circuit or a battery circuit connected to a memory cell or logic circuit, the first interconnection layer 4 is connected to a second thin interconnection 15 at a through hole 17. The interconnection structure incorporating the through hole 17 provides a less reliable electrical connection than the interconnection structure employing the through hole 16. Referring to FIGS. 46(A) and 46(B), the current I1 flows from the first interconnection layer 4 to the second thin interconnection 15 through the through hole 17. A void 201 may be produced in the first interconnection layer 4 at the through hole 17 by electromigration.
Electromigration is explained with respect to FIGS. 47(A)-49(B), plan and section views corresponding to FIGS. 45(A) and 45(B). It is known that the aluminum alloy film 311 has a polycrystalline structure containing randomly disposed minute defects. The quantity of the defects depends upon the conditions of the formation of the aluminum alloy film. As the width of the interconnection increases, the number of defects per unit length increases. When the current I1 flows from the first interconnection layer 4 to the second thinner connection 15 through the through hole 17, electrons 203 flow from the aluminum alloy film 10 to the aluminum alloy 311. The flowing electrons are scattered by grain boundaries 204 in the aluminum films, dislodging aluminum atoms and causing those atoms to migrate. Thus, the minute defects 202 in the aluminum alloy film 311 grow gradually, producing new defects at the locations from which aluminum atoms migrate. As this process is repeated, the defects 202 become larger defects 205. The defects 205 tend to form in clusters and create voids where the carrier mobility of the material changes significantly as compared to the remainder of the material. In the interconnection structure shown in FIGS. 47(A) and 48(A), the large defects 205 gather near the through hole 17 in the film 311.
The mobility of the atoms in the aluminum alloy layer 311 is much larger than the mobility of the atoms in the titanium nitride film 9. A void that is produced by the collection of the defects 202 causes deterioration of the layer 311 adjacent the through hole 17. The likelihood that this defect phenomenon will occur is increased by the large difference between the mobility of atoms in the two materials of the respective films. Moreover, because the number of the defects in the first interconnection layer 4 is larger than the number of defects in the narrow interconnection 12, the void produced at the through hole 17 will be larger than the void produced at the through hole 16.
The effect of the defects on the through hole increases as the size of the through hole decreases. Therefore, the adverse effects of electromigration are reduced when the interconnection is narrower or when the through hole is relatively large in size. In other words, it is more difficult to interrupt an electrical connection at through hole 16 than at through hole 17. Ultimately, an electrical interconnection with a void can completely fail and become electrically open. However, until the electrical interconnection fails, it increases in resistance. Although particular interconnections including two different interconnections, each comprising two different metal films, have been described, the same phenomenon occurs in interconnections so long as different materials are in contact.
In FIGS. 50(A) and 50(B), which are a plan view and a sectional view taken along line 50(B)--50(B) of FIG. 50(A), respectively, the DRAM cell 2 is disposed on the silicon substrate 1. The first dielectric layer 3 is disposed on the DRAM cell 2 and a tungsten polycide interconnection layer 21 is disposed at spaced apart intervals on the first dielectric layer 3. The tungsten polycide interconnection layer 21 includes a film 21a of polycrystalline silicon on which is disposed a tungsten silicide film 21b. The second dielectric layer 5 covers the tungsten polycide interconnection layer 21. The through hole 6 penetrates the second dielectric layer 5. An aluminum interconnection layer 22 is disposed on the second dielectric layer 5 and is connected to the tungsten polycide interconnection layer 21 through the through hole 6. The third dielectric layer 8 covers the DRAM cell 2, the tungsten polycide interconnection layer 21, and the aluminum interconnection layer 22 to prevent moisture from entering the structure.
As shown in FIG. 51, in this structure, a current I3 flows from the wide tungsten polycide interconnection layer 21 at the left side of FIG. 50(A) to the relatively wide aluminum interconnection layer 22 through the small through hole 6. In this case, defects in the aluminum layer 22 move by electromigration and collect at the through hole 6 to produce the void 201. As a result, the interconnection becomes electrically open. The electromigration phenomenon occurs whenever the materials in contact as part of the interconnection are different. In this way, whenever there is a contact interface between different materials, there is a very large difference in the mobility of atoms within the materials as a result of the contact interface. This difference in mobility is of no concern if the through hole is relatively large. However, at submicron through hole sizes, the difference in mobility is a serious problem because of the possibility of producing open circuits.
The present invention is directed to solving the problem of increased resistance and open circuits in multi-level interconnections in semiconductor integrated circuits. In particular, it is an object of the invention to provide an interconnection between electrically conducting lines of different materials without producing interconnections of increasing resistance or open circuits, thereby increasing the reliability of an integrated circuit incorporating the interconnection.